QDNix
Quick’n’dirty *NIX
8250.h
1 /*
2  * BSD 3-Clause License
3  *
4  * Copyright (c) 2022, d0p1
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice, this
11  * list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  * this list of conditions and the following disclaimer in the documentation
14  * and/or other materials provided with the distribution.
15  *
16  * 3. Neither the name of the copyright holder nor the names of its
17  * contributors may be used to endorse or promote products derived from
18  * this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
27  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
28  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _SYS_DEV_SERIAL_8250_H
33 # define _SYS_DEV_SERIAL_8250_H 1
34 
35 /* UART 8250 , 16750 */
36 
37 # define UART8250_RBR 0x0 /* RX */
38 # define UART8250_THR 0x0 /* TX */
39 
40 # define UART8250_IER 0x1
41 # define UART8250_IER_RDA 0x1
42 # define UART8250_IER_THRE 0x2
43 # define UART8250_IER_RLSRC 0x4
44 # define UART8250_IER_MSRC 0x8
45 
46 /* 16750 only */
47 # define UART16750_IER_SLEEP 0x10
48 # define UART16750_IER_LPM 0x20
49 
50 # define UART8250_IIR 0x2
51 
52 # define UART8250_FCR 0x2
53 # define UART8250_FCR_EN 0x1
54 # define UART8250_FCR_CLSR 0x2
55 # define UART8250_FCR_CLST 0x4
56 # define UART8250_FCR_DMA 0x8
57 
58 /* 16750 only */
59 # define UART16750_FCR_64EN 0x20
60 
61 # define UART8250_LCR 0x3
62 
63 # define UART8250_MCR 0x4
64 
65 # define UART8250_LSR 0x5
66 
67 # define UART8250_MSR 0x6
68 
69 # define UART8250_SCR 0x7
70 
71 /* DLAB == 1 */
72 # define UART8250_DLL 0x0
73 
74 # define UART8250_DLH 0x1
75 
76 #endif /* !_SYS_DEV_SERIAL_8250_H */